1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, it relates to a semiconductor memory device comprising switching transistors and charge storage capacitors arranged above the switching transistors and also to a method of manufacturing this semiconductor memory device.
2. Description of the Related Art
Owning to the advancement of integration-circuit technology, semiconductor memories are made smaller and smaller. Capacitors, which are circuit elements indispensable to a semiconductor memory, should therefore be made as small as possible. To form small capacitors in a high density, two methods have hitherto been employed. The first method is to make grooves in the same substrate in which active elements such as transistors are formed and then form charge storage layers in the grooves, forming trench capacitors. The second method is to form charge storage layers, one upon another, on a substrate, forming stacked capacitors. Either method provides a relatively large charge storage area.
Thin-film capacitors have not been made as small as desired, unlike the active elements such as switching transistors. Consequently, it is difficult to increase the integration density of semiconductor memories. Thin-film capacitors cannot be miniaturized because they are made of dielectric material having a dielectric constant of 10 at the most, such as SiO.sub.2 and Si.sub.3 N.sub.4. To provide smaller thin-film capacitors it is necessary to develop and use dielectric material which has a high dielectric constant.
Known as materials having a high dielectric constant are perovskite oxides such as SrTiO.sub.3, BaTiO.sub.3, PbTiO.sub.3 and PbZrO.sub.3. More specifically, they are known to have dielectric constants ranging from 100 to 1000, either singly or in combination (i.e., a solid solution). Therefore, they are used as materials of ceramic capacitors. Thin film of a perovskite oxide is useful in providing small thin-film capacitors. Researches have long been conducted on thin-film capacitors made of perovskite oxides, showing that these thin-film capacitors have relatively good characteristics.
Thin film having a high dielectric constant, such as SrTiO.sub.2 thin film, can be formed at high temperature only. It is formed on electrodes of noble metal such as platinum, palladium and gold or an oxide thereof. Electrodes made of noble metal or an oxide thereof can hardly be used in various integrated circuits (e.g., memory-cell arrays), most of which are formed on silicon substrates. The reasons are as follows:
The primary reason is that no satisfactory processing technology has been established to form small electrodes of noble metal or an oxide thereof since the vapor pressure of any halogen compound of noble metal is far less than desired for performing photolithography and plasma etching on film of noble metal or an oxide thereof. Various methods of forming thin-film capacitors by using material having a high dielectric constant are known. In the method disclosed in Jpn. Pat. Appln. KOKAI Publication No. 4-80952, a bottom electrode, a film having a high dielectric constant, and a top electrode are deposited, one upon another, on the inter-layer insulating film formed on element-isolating film, bit lines and word lines. In the method disclosed in Jpn. Pat. Appln. KOKAI Publication No. 3-256358, a thin-film capacitor is formed on a flat insulating film. In the method disclosed in Jpn. Pat. Appln. KOKAI Publication No. 4-206569, a film having a high dielectric constant is formed on the flat upper surface of a bottom electrode. In all these methods exemplified, an electrically conductive film is processed in a micro-pattern by means of photolithography and plasma etching. Since the bottom electrodes are formed by photolithography and plasma etching in these known methods, it will be difficult to provide reliable bottom electrodes for an integrated circuit at a sufficiently high yield if the bottom electrodes are made from film of noble metal or an oxide thereof.
When thin-film capacitors including film having a high dielectric constant are used to increase the integration density of the integrated circuit, the capacitors must be arranged three-dimensionally so that each capacitor may accumulate great amount of electric charge. To arrange the capacitors so, it is necessary to provide micro-patterning of bottom electrodes. However, processing technology capable of forming such micro-patterned electrodes has not been established yet, as mentioned above.
FIG. 1 shows a known memory cell having a trench capacitor. In the surface of an Si substrate 1 of a first conductivity type, there are formed impurity regions 6a and 6b of the second conductivity type. A gate-insulating film 3 is provided on the impurity regions 6a and 6b and that portion of the Si substrate 1 which lies between the impurity regions 6a and 6b. A word line 4 is provided on the gate insulating film 3. That portion of the Si substrate 1, the gate insulating film 3, the impurity regions 6a and 6b, and the word line 4 constitute a transistor. A trench is made in the Si substrate 1, located near the transistor. A silicon bottom electrode 43, a thermally-oxidized silicon dielectric layer 44, and a top electrode 15 are formed, one upon another, in the trench, forming the trench capacitor. The trench capacitor is connected to the impurity region 6b, whereas a bit line 8 is connected to the impurity region 6a. The memory cell of FIG. 1 further comprises an inter-layer insulating film 7 and an insulating film 9. The film 9 is the top layer of the structure, having a flat upper surface. Where a high dielectric constant film is used in this memory cell, it has the drawback that Ba, Sr or Pb contained in the high dielectric constant film 14 and the noble metal (e.g., Pt) forming the bottom electrode 13 would diffuse into the impurity regions 6a and 6b.
FIG. 2 shows a known memory cell having a stacked capacitor. As shown in FIG. 2, a capacitor having a convex shape and comprised of a bottom electrode 13, a high dielectric constant film 14 and a top electrode 15 is located above a Si substrate 1. A transistor is formed of a portion of the Si substrate 1, a gate-insulating film 3, impurity regions 6a and 6b and the word line 4. The capacitor and the transistor are isolated from each other by an insulating layer. The high dielectric constant film 14 is used in place of conventional utilized silicon oxide film or silicon nitride film, either conventionally utilized. The film 14 is deposited on the convex surface. If formed by sputtering or chemical vapor deposition (CVD), the high dielectric constant film 14 fails to have a uniform thickness.